1. Field of the Invention
The present invention relates to the technical field of chip-to-chip signal transmission and, more particularly, to a chip-to-chip multi-signaling communication system with common conductive layer.
2. Description of Related Art
With the rapid development of consumer products such as wireless networks, digital multimedia and the like, multiple modules are needed to be integrated into a single chip for system-on-chip (SoC), so as to relatively increase the complexity of the design of SoC. The concept for designing the SoC has faced lots of difficulty such as: the increasing chip area with the complexity, the parameter shifting of the chip, and the difficulty of integrating different fabricating techniques. The factors mentioned above are the principle reasons that the yield rate cannot be increased. At the same time, due to progress in packaging techniques for chips, SoC integration has turned from planar integration into 3D IC technology. 3D IC technology has already become the most plausible option for current IC industries to meet Moore's Law.
The 3D IC technology that developed currently was to reach the hetero-chip integration by stacking chips fabricated in different processes while in packaging stage. 3D IC technology, which is to integrate multiple chips vertically in three-dimensional space, was developed in order to achieve the most benefit for minimal size. Vertical conduction configuration is employed in 3D IC technology and is different from planar chip integration. In this case, the connection length and delay time between transistors are obviously shorter than the conventional 2D circuit. In addition, the chip performance is increased and the power consumption is reduced. Further, the noise coupling caused by the inductive and capacitive effects is much lower.
The 3D IC technology at present is generally system in package (SIP), which comprises technology such as stack die and flip-chip.
Although different types of chip connection are used in the typical 3D IC technology, for signal transmission, conventional point-to-point type is served. For example, FIG. 1 is a perspective view of a traditional 3D IC configuration with wire bonding. As shown in FIG. 1, wires 11 are incorporated for the connection between the chip 12 and the substrate 13. A large amount of space on a chip is required by the wires for wire bonding, which causes a large number of interconnections to be impossible, which in turn creates heavier load effect, and longer transmission distance have occurred.
FIG. 2 is a perspective view of a typical 3D IC configuration with solder bonding of a flip chip technology. As shown in FIG. 2, the upper chip 21 connects with the lower chip 22 through the solder balls 23. Though the flip chip technology contains shorter distance connection (10-15 μm) and higher density connection, the problems of temperature and filling also exist in the back-end process, which therefore results in low yield rate and high cost expenditure.
Additionally, the capacitive coupling and the inductive coupling form the chip-to-chip connection which requires a larger metal area for on-chip capacitors and inductors. Complex circuit design for transmitter and receiver is another important issue. Further, the alignment of pads is also a problem.
No matter wire bonding technology, flip chip technology, or capacitive coupling and inductive coupling connection technology, their common purpose is to form the point-to-point signal communication path between the chips. Thus the traditional chip-to-chip communication system needs to be improved due to the disadvantages already mentioned above.